library ieee;
use ieee.std_logic_1164.all;

--H_Load, L_Load are active high
--clr and hold are active low
--loads must be off to clear or shift
entity productReg is
	port (
		H_in, L_in : in bit_vector(31 downto 0);
		clk, clr, H_load, L_load, H_Hold, L_Hold : in bit;
		H_out, L_out : out bit_vector(31 downto 0);
		a_1 : out bit
	);
end entity productReg;
	
architecture STRUCTURAL of productReg is
	
	component SR32
		port (
			clk, clr, load, hold, serialIn : in bit;
			inVec : in bit_vector(31 downto 0);
			outVec : out bit_vector(31 downto 0)
		);
	end component;
	
	component SR
		port (
			clk, dataIn, QInPrev, selectH, selectL: in bit;
			R : out bit
		);
	end component;

	component SRselect
		port(
			clk, clr, load, hold : in bit;
			z1, z2 : out bit
		);
	end component;	

	for all : SR32 use entity work.ShiftRegister32(STRUCTURAL);
	for all : SR use entity work.shiftRegModule(STRUCTURAL);
	for all : SRselect use entity work.shiftRegSelectLogic(STRUCTURAL);
	
	signal slct : bit_vector(1 downto 0);
	signal C_hold : bit;
	signal TempH_out, TempL_out : bit_vector(31 downto 0);
	
	begin
		
		C_hold <= H_hold or L_hold;
		high_SR : SR32 port map (clk, clr, H_load, H_hold, TempH_Out(31), H_in, TempH_out);
		low_SR : SR32 port map(clk, clr, L_load, L_hold, TempH_out(0), L_in, TempL_out); 
		select_logic : SRselect port map(clk, clr, '0', C_hold, slct(1), slct(0));
		compare_bit : SR port map(clk, '0', TempL_out(0), slct(1), slct(0), a_1);
		
		H_out <= TempH_out;
		L_out <= TempL_out;

end architecture STRUCTURAL;
